NVIDIA deploys Vera CPU with Cadence and Synopsys to accelerate chip design EDA

NVIDIA said it is collaborating with Cadence and Synopsys to optimize critical electronic design automation applications for the NVIDIA Vera CPU, and is deploying Vera across EDA workflows used to develop its next generation of CPUs and GPUs. While GPUs and AI have sped many chip design steps, the company said several critical EDA workloads remain heavily dependent on CPU performance, including logic simulation, formal verification and portions of digital implementation that rely on fast individual cores, efficient memory systems and strong throughput. Early testing on selected production-class workflows showed up to 1.5x higher performance on Cadence Jasper, a formal verification platform, and Synopsys VCS, a functional verification solution that used the same number of cores in the test, NVIDIA said. The company is also working with both vendors on application profiling, software optimization and system-level tuning. Vera combines 88 custom NVIDIA Olympus CPU cores with a high-efficiency LPDDR5X memory subsystem and second generation NVIDIA Scalable Coherent Fabric, aimed at strong per-core performance, high memory bandwidth and consistent low latency for demanding engineering applications, according to the NVIDIA Blog. NVIDIA said the same Vera systems used for simulation and verification are also being applied to place-and-route, timing analysis and physical verification stages after RTL definition. The company framed the work as using its own next-generation CPU architecture inside the design process that produces future NVIDIA processors.