Synopsys Introduces Software-Defined Hardware-Assisted Verification to Enable AI Proliferation

Synopsys Inc. announced advancements across its hardware-assisted verification portfolio to support the demand for artificial intelligence chip verification from data center to edge applications. The updates include software-defined capabilities that deliver up to a 2 times performance boost for ZeBu Server 5 and scale capacity up to 2 times with modular hardware-assisted verification for large designs. New HAPS-200 12 FPGA and ZeBu-200 12 FPGA platforms feature EP-Ready Hardware that extends capacity by 2 times while providing leading performance. The company introduced industry-first hardware-assisted test automation capabilities that enable faster and earlier detection of cache-coherency and subsystem-level bugs. These advancements target the needs of data center, mobile, client, server, consumer and edge artificial intelligence applications. Ravi Subramanian, chief product management officer at Synopsys, said that building high confidence early that the workloads are running to spec on the silicon under development is critical. He stated that the software-defined hardware-assisted verification solutions deliver continuous innovation and act as a force multiplier to scale verification productivity. Salil Raje, senior vice president and general manager of the adaptive and embedded computing group at AMD, said hardware-assisted verification is critical to meeting aggressive time-to-market goals and ensuring silicon readiness. Narendra Konda, vice president of hardware engineering at NVIDIA, said the new systems are accelerating system-level verification and validation to help deliver complex artificial intelligence platforms on aggressive schedules. Software-defined enhancements are being rolled out continuously across the portfolio and are available to users today. The new EP-Ready HAPS-200 12 FPGA platform is available today while the ZeBu-200 12 FPGA platform is scheduled for Q3 2026.