# Tesla outlines chiplet and stacked-memory design for Dojo D3

_Published Friday, November 6, 2026 at 7:18 AM EST · AI, Infrastructure · Latest · Tier 2 — Notable_

![Tesla — Primary](https://cdn.mos.cms.futurecdn.net/c7SXsstwCWqWGyvTD7KQAA-1920-80.jpg)

Tesla disclosed a revised accelerator roadmap that describes its Dojo D3 training chip as a chiplet-based design using stacked high-bandwidth memory. The planned design departs from Dojo D1, which connected processors through wafer-scale packaging and relied on memory built into the chips.

Tesla also projects that its SI6 inference accelerator, due in 2029-2030, will deliver 80 times HW4's compute performance. D3 remains in development, and Tesla has not disclosed its compute performance, memory capacity, manufacturing process or development schedule.

## Sources

- [Tom's Hardware](https://www.tomshardware.com/tech-industry/artificial-intelligence/tesla-unveils-ai-accelerator-roadmap-adopts-new-si-branding-in-super-intelligence-push-si6-to-bring-80x-more-compute-performance-dojo-3-headed-to-space)

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Canonical: https://techandbusiness.org/newswire/aav4kHsZY-n6MSSkbW1Qmi
Published: 2026-11-06T12:18:21.418Z
Story chronology: 2026-11-06T12:00:00.000Z
Retrieved: 2026-11-06T23:11:24.111Z
Publisher: Tech & Business (techandbusiness.org)