# Microsoft details Maia 300 chip design for larger AI inference workloads

_Published Tuesday, October 13, 2026 at 3:26 PM EDT · AI, Infrastructure · Latest · Tier 2 — Notable_

![Microsoft details Maia 300 chip design for larger AI inference workloads — Primary](https://image.nextplatform.com/5302877.jpg?imageId=5302877&x=0&y=0&cropw=100&croph=100&panox=0&panoy=0&panow=100&panoh=100&width=1200&height=683)

Microsoft disclosed specifications for its future Maia 300 accelerator as the Open Compute Project Summit opened this week. The chip targets AI inference, the computation that produces model outputs, and larger workloads in which multiple models share memory and network capacity.

The design moves from monolithic chips to a package of seven chips and eight high-bandwidth memory stacks, separating input-output and memory controllers from compute and cache components. It provides 288 GB of HBM4 memory and 18 TB/sec of memory bandwidth. Microsoft also changed its accelerator network to fit more devices into racks and interconnected groups. Maia 200, rather than Maia 300, is the generation ramping into Azure production this year.

## Sources

- [The Next Platform: In-depth coverage of high end computing](https://www.nextplatform.com/compute/2026/10/13/microsofts-clea-maia-300-inference-xpu-is-a-bandwidth-beast/5302874)

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Canonical: https://techandbusiness.org/newswire/bx4VfNt0hkdku89hy1G-Od
Published: 2026-10-13T19:26:28.988Z
Story chronology: 2026-10-13T18:17:46.000Z
Retrieved: 2026-10-13T21:53:39.446Z
Publisher: Tech & Business (techandbusiness.org)