# XCENA and Samsung describe CXL memory device with onboard compute

_Sunday, August 30, 2026 at 3:35 AM EDT · Infrastructure · Latest · Tier 2 — Notable_

![XCENA and Samsung describe CXL memory device with onboard compute — Primary](https://substackcdn.com/image/fetch/$s_!rmOv!,w_1200,h_675,c_fill,f_jpg,q_auto:good,fl_progressive:steep,g_auto/https%3A%2F%2Fsubstack-post-media.s3.amazonaws.com%2Fpublic%2Fimages%2Fc4f3c070-692f-4557-9569-ea6f1d9fb689_1273x713.png)

XCENA and Samsung have described MX1, a CXL memory-expansion device that combines up to 2 TB of DDR5 memory, SSD connectivity and onboard compute. The device connects through PCIe 6/CXL 3.2 x8 and includes 3,072 RISC-V cores plus vector-processing hardware. Its SSDs can be exposed as memory, with attached DRAM acting as a cache. XCENA's approach is designed to run data-parallel work near the expanded memory pool, reducing reliance on the bandwidth-constrained host link for those workloads.

## Sources

- [Chips and Cheese](https://chipsandcheese.com/p/hot-chips-2026-xcena-and-samsungs)

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Canonical: https://techandbusiness.org/newswire/efCigpjkzU_nT43Wqi34aG
Retrieved: 2026-08-30T12:02:07.473Z
Publisher: Tech & Business (techandbusiness.org)