# Qwenputer prototype embeds a processor in an AI model to run code

_Published Monday, November 2, 2026 at 9:06 AM EST · AI · Latest · Tier 2 — Notable_

![RISC-V Prototype — Primary](https://cdn.mos.cms.futurecdn.net/vDamaQXjMra2LE6RAc87N6-1920-80.jpg)

AI engineer Divyansh Agrawal has released Qwenputer, an experimental modification of Qwen 3.5 4B that runs C and MicroPython code through a processor embedded in the model, without external runtime calls. The model is available on Hugging Face, with MIT-licensed code on GitHub.

A compiler generates 11 additional transformer layers implementing a 32-bit RISC-V processor. The model uses its DeltaNet state as working memory and filesystem storage. Agrawal says the processor passed official RISC-V tests and ran 18 million instructions without an error. The modified model occupies almost 19GB; Agrawal recommends at least 24GB of video memory for testing.

## Sources

- [Tom's Hardware](https://www.tomshardware.com/tech-industry/artificial-intelligence/ai-engineer-successfully-compiles-a-32-bit-risc-v-cpu-in-qwen-3-5-4b-llm-inserted-directly-into-its-weights-built-in-cpu-can-run-processor-arithmetic-operations-code-and-of-course-doom)

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Canonical: https://techandbusiness.org/newswire/vRvDXL1jAUL8JkPUQ_K-ac
Published: 2026-11-02T14:06:42.009Z
Story chronology: 2026-11-02T13:30:00.000Z
Retrieved: 2026-11-02T17:08:13.444Z
Publisher: Tech & Business (techandbusiness.org)