Tesla outlines chiplet and stacked-memory design for Dojo D3

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Published Friday, November 6, 2026 · 7:18 AM EST

Tesla disclosed a revised accelerator roadmap that describes its Dojo D3 training chip as a chiplet-based design using stacked high-bandwidth memory. The planned design departs from Dojo D1, which connected processors through wafer-scale packaging and relied on memory built into the chips. Tesla also projects that its SI6 inference accelerator, due in 2029-2030, will deliver 80 times HW4's compute performance. D3 remains in development, and Tesla has not disclosed its compute performance, memory capacity, manufacturing process or development schedule.

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