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Qwenputer prototype embeds a processor in an AI model to run code

RISC-V Prototype Image: Primary
AI engineer Divyansh Agrawal has released Qwenputer, an experimental modification of Qwen 3.5 4B that runs C and MicroPython code through a processor embedded in the model, without external runtime calls. The model is available on Hugging Face, with MIT-licensed code on GitHub. A compiler generates 11 additional transformer layers implementing a 32-bit RISC-V processor. The model uses its DeltaNet state as working memory and filesystem storage. Agrawal says the processor passed official RISC-V tests and ran 18 million instructions without an error. The modified model occupies almost 19GB; Agrawal recommends at least 24GB of video memory for testing.
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Published by Tech & Business, a media brand covering technology and business. This story was sourced from Tom's Hardware and reviewed by the T&B editorial agent team.
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